drifty/emulator
1
0
Fork 0
mirror of https://git.citron-emu.org/citron/emulator synced 2025-12-19 10:43:33 +00:00
Code Issues Packages Projects Releases Wiki Activity

Revert "shader_recompiler: Implement ISBERD instruction"

Browse Source 
This reverts commit d2c6f3ab9c.
This commit is contained in:
Zephyron
2025-09-14 18:19:36 +10:00
parent 3c70fd52bd
commit ce06115c2c
1 changed files with 4 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
src/shader_recompiler/frontend/maxwell/translate/impl/internal_stage_buffer_entry_read.cpp
View File

@@ -1,5 +1,4 @@
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-FileCopyrightText: Copyright 2025 citron Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later // SPDX-License-Identifier: GPL-2.0-or-later
#include "common/bit_field.h" #include "common/bit_field.h"
@@ -40,55 +39,14 @@ void TranslatorVisitor::ISBERD(u64 insn) {
if (isberd.o != 0) { if (isberd.o != 0) {
throw NotImplementedException("O"); throw NotImplementedException("O");
} }
if (isberd.mode != Mode::Default) {
// Get the source register value as the buffer index
const IR::U32 buffer_index{X(isberd.src_reg)};
// Read from the internal stage buffer based on mode
IR::F32 result_f32;
switch (isberd.mode) {
case Mode::Default:
// Default mode: read from stage buffer using the index
result_f32 = ir.GetAttributeIndexed(buffer_index);
break;
case Mode::Patch:
// Patch mode: read patch data
result_f32 = ir.GetPatch(static_cast<IR::Patch>(buffer_index.U32()));
break;
case Mode::Prim:
// Prim mode: read primitive data
result_f32 = ir.GetAttributeIndexed(buffer_index);
break;
case Mode::Attr:
// Attr mode: read attribute data
result_f32 = ir.GetAttributeIndexed(buffer_index);
break;
default:
throw NotImplementedException("Mode {}", isberd.mode.Value()); throw NotImplementedException("Mode {}", isberd.mode.Value());
} }
if (isberd.shift != Shift::Default) {
// Convert float result to unsigned integer
IR::U32 result = ir.ConvertFToU(32, result_f32);
// Apply shift operation if specified
switch (isberd.shift) {
case Shift::Default:
// No shift needed
break;
case Shift::U16:
// Shift right by 16 bits
result = ir.ShiftRightLogical(result, ir.Imm32(16));
break;
case Shift::B32:
// Shift right by 32 bits
result = ir.ShiftRightLogical(result, ir.Imm32(32));
break;
default:
throw NotImplementedException("Shift {}", isberd.shift.Value()); throw NotImplementedException("Shift {}", isberd.shift.Value());
} }
LOG_WARNING(Shader, "(STUBBED) called");
// Store result in destination register X(isberd.dest_reg, X(isberd.src_reg));
X(isberd.dest_reg, result);
} }
} // namespace Shader::Maxwell } // namespace Shader::Maxwell