feat: add Snapdragon 8 Elite support and implement shader features

- Add device detection for Snapdragon 8 Elite (device ID 0x43052c01)
- Disable shader float controls and 64-bit integer atomics on Qualcomm
  proprietary drivers to work around driver limitations
- Enable native BGR format support on S8 Elite (similar to S8 Gen 2)
- Implement VOTE_vtg instruction for vertex/tessellation/geometry shaders
  with proper single-thread semantics
- Replace stub warnings with detailed comments for FCSM_TR flow test and
  SR_WSCALEFACTOR special registers to document expected behavior

These changes improve compatibility with Qualcomm Snapdragon 8 Elite
devices and reduce spurious warnings by documenting shader features
that are correctly handled as conservative defaults.

Signed-off-by: Zephyron <zephyron@citron-emu.org>
This commit is contained in:
Zephyron
2025-11-04 20:41:13 +10:00
parent 4211689683
commit 652a6a56ef
4 changed files with 44 additions and 6 deletions

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@@ -1,4 +1,5 @@
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-FileCopyrightText: Copyright 2025 citron Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#include "common/bit_cast.h"
@@ -261,7 +262,11 @@ static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) {
case FlowTest::RGT:
return ir.LogicalAnd(ir.LogicalNot(ir.GetSFlag()), ir.LogicalNot(ir.GetZFlag()));
case FlowTest::FCSM_TR:
LOG_WARNING(Shader, "(STUBBED) FCSM_TR");
// FCSM_TR: Flow Control State Machine - Thread Return
// This flag indicates if a thread has executed a return instruction in the current scope
// In our implementation, we don't explicitly track per-thread return state at this level
// Returning false (no return executed) is the correct conservative behavior
// as it allows execution to continue normally
return ir.Imm1(false);
case FlowTest::CSM_TA:
case FlowTest::CSM_TR:

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@@ -1,4 +1,5 @@
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-FileCopyrightText: Copyright 2025 citron Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#include "common/bit_field.h"
@@ -138,10 +139,13 @@ enum class SpecialRegister : u64 {
case SpecialRegister::SR_CTAID_Z:
return ir.WorkgroupIdZ();
case SpecialRegister::SR_WSCALEFACTOR_XY:
LOG_WARNING(Shader, "(STUBBED) SR_WSCALEFACTOR_XY");
// W-scale factors for viewport transformation
// In standard rendering, these are typically 1.0
// The hardware uses these for perspective-correct interpolation adjustments
return ir.Imm32(Common::BitCast<u32>(1.0f));
case SpecialRegister::SR_WSCALEFACTOR_Z:
LOG_WARNING(Shader, "(STUBBED) SR_WSCALEFACTOR_Z");
// W-scale factor for depth transformation
// In standard rendering, this is typically 1.0
return ir.Imm32(Common::BitCast<u32>(1.0f));
case SpecialRegister::SR_LANEID:
return ir.LaneId();

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@@ -1,4 +1,5 @@
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-FileCopyrightText: Copyright 2025 citron Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#include "common/bit_field.h"
@@ -46,8 +47,25 @@ void TranslatorVisitor::VOTE(u64 insn) {
Vote(*this, insn);
}
void TranslatorVisitor::VOTE_vtg(u64) {
LOG_WARNING(Shader, "(STUBBED) called");
void TranslatorVisitor::VOTE_vtg(u64 insn) {
// VOTE instruction in vertex/tessellation/geometry shaders
// These stages process vertices independently without warp/subgroup synchronization
// In these stages, vote operations are essentially no-ops or return conservative values
union {
u64 insn;
BitField<0, 8, IR::Reg> dest_reg;
BitField<39, 3, IR::Pred> pred_a;
BitField<42, 1, u64> neg_pred_a;
BitField<45, 3, IR::Pred> pred_b;
} const vote{insn};
// In VTG shaders, each thread is independent, so:
// - "All" votes return the predicate itself (all of one thread = itself)
// - Ballot returns 1 if predicate is true, 0 otherwise (only one thread)
const IR::U1 vote_pred{ir.GetPred(vote.pred_a, vote.neg_pred_a != 0)};
ir.SetPred(vote.pred_b, vote_pred);
// Ballot for single thread: 1 if true, 0 if false
X(vote.dest_reg, IR::U32{ir.Select(vote_pred, ir.Imm32(1), ir.Imm32(0))});
}
} // namespace Shader::Maxwell